Invention Grant
- Patent Title: Anti-fuse cell structure including reading and programming devices with different gate dielectric thickness
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Application No.: US15004329Application Date: 2016-01-22
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Publication No.: US10014066B2Publication Date: 2018-07-03
- Inventor: Jhon Jhy Liaw , Shien-Yang Wu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: G11C17/00
- IPC: G11C17/00 ; G11C17/18 ; H01L23/525 ; H01L23/528 ; H01L29/78 ; H01L29/94 ; G11C17/16 ; H01L27/112

Abstract:
A structure includes a word-line, a bit-line, and an anti-fuse cell. The anti-fuse cell includes a reading device, which includes a first gate electrode connected to the word-line, a first gate dielectric underlying the first gate electrode, a drain region connected to the bit-line, and a source region. The first gate dielectric has a first thickness. The drain region and the source region are on opposite sides of the first gate electrode. The anti-fuse cell further includes a programming device including a second gate electrode connected to the word-line, and a second gate dielectric underlying the second gate electrode. The second gate dielectric has a second thickness smaller than the first thickness. The programming device further includes a source/drain region connected to the source region of the reading device.
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