Invention Grant
- Patent Title: MOS-gated power devices, methods, and integrated circuits
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Application No.: US14603181Application Date: 2015-01-22
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Publication No.: US10014404B2Publication Date: 2018-07-03
- Inventor: Mohamed N. Darwish , Jun Zeng
- Applicant: MaxPower Semiconductor, Inc.
- Applicant Address: US CA San Jose
- Assignee: MaxPower Semiconductor Inc.
- Current Assignee: MaxPower Semiconductor Inc.
- Current Assignee Address: US CA San Jose
- Agency: Groover & Associates PLLC
- Agent Gwendolyn G. Corcoran; Robert O. Groover, III
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/78 ; H01L29/06 ; H01L29/10 ; H01L29/40 ; H01L29/49 ; H01L29/08 ; H01L29/423

Abstract:
MOS-gated devices, related methods, and systems for vertical power and RF devices including an insulated trench and a gate electrode. A body region is positioned so that a voltage bias on the gate electrode will cause an inversion layer in the body region. Permanent electrostatic charges are included in said insulation material. A conductive shield layer is positioned above the insulated trench, to reduce parasitic capacitances.
Public/Granted literature
- US20150214350A1 MOS-Gated Power Devices, Methods, and Integrated Circuits Public/Granted day:2015-07-30
Information query
IPC分类: