- Patent Title: Method for producing semiconductor device and semiconductor device
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Application No.: US15505563Application Date: 2014-12-02
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Publication No.: US10014410B2Publication Date: 2018-07-03
- Inventor: Tadashi Yamaguchi
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: McGinn IP Law Group, PLLC
- International Application: PCT/JP2014/081839 WO 20141202
- International Announcement: WO2016/088196 WO 20160609
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L29/78 ; H01L27/11568 ; H01L27/11573 ; H01L29/66 ; H01L21/285

Abstract:
A silicide layer on a gate electrode of a MONOS memory is prevented from being disconnected, and a property of a MISFET is improved. As means for that, when a memory cell and a MISFET formed by so-called gate-last process are mixedly mounted, a silicide layer on a source/drain region is formed by a salicide process with relatively high temperature heat treatment, and then, a silicide layer is formed on each of the control gate electrode and the memory gate electrode of the memory cell by a salicide process with relatively low temperature heat treatment.
Public/Granted literature
- US20170271513A1 METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE Public/Granted day:2017-09-21
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