Invention Grant
- Patent Title: Dual liner CMOS integration methods for FinFET devices
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Application No.: US15647453Application Date: 2017-07-12
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Publication No.: US10026655B2Publication Date: 2018-07-17
- Inventor: Min Gyu Sung , Chanro Park , Ruilong Xie , Hoon Kim
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Amerson Law Firm, PLLC
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L27/092
Abstract:
An integrated circuit product includes an NFET FinFET device having a first fin that is made entirely of a first semiconductor material and a PFET FinFET device that includes a second fin having an upper portion and a lower portion, wherein the lower portion is made of the first semiconductor material and the upper portion is made of a second semiconductor material that is different from the first semiconductor material. A silicon nitride liner is positioned on and in contact with the lower portion of the second fin, wherein the silicon nitride liner is not present on or adjacent to the upper portion of the second fin or on or adjacent to any portion of the first fin.
Public/Granted literature
- US20170316985A1 DUAL LINER CMOS INTEGRATION METHODS FOR FINFET DEVICES Public/Granted day:2017-11-02
Information query
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