Invention Grant
- Patent Title: Low defect III-V semiconductor template on porous silicon
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Application No.: US14645449Application Date: 2015-03-12
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Publication No.: US10032870B2Publication Date: 2018-07-24
- Inventor: Joel P. de Souza , Keith E. Fogel , Alexander Reznicek , Dominic J. Schepis
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Hoffman Warnick LLC
- Agent Yuanmin Cai
- Main IPC: H01L29/20
- IPC: H01L29/20 ; H01L29/16 ; H01L21/02 ; H01L29/36

Abstract:
A method of forming a semiconductor on a porous semiconductor structure. The method may include forming a stack, the stack includes (from bottom to top) a substrate, a base silicon layer, a thick silicon layer, and a thin silicon layer, where the thin silicon layer and the thick silicon layer are relaxed; converting the thick silicon layer into a porous silicon layer using a porousification process; and forming a III-V layer on the thin silicon layer, where the III-V layer is relaxed, the thin silicon layer is strained, and the porous silicon layer is partially strained.
Public/Granted literature
- US20160268123A1 LOW DEFECT III-V SEMICONDUCTOR TEMPLATE ON POROUS SILICON Public/Granted day:2016-09-15
Information query
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