Invention Grant
- Patent Title: CMOS-MEMS integrated device with selective bond pad protection
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Application No.: US15356916Application Date: 2016-11-21
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Publication No.: US10035702B2Publication Date: 2018-07-31
- Inventor: Daesung Lee
- Applicant: INVENSENSE, INC.
- Applicant Address: US CA San Jose
- Assignee: INVENSENSE, INC.
- Current Assignee: INVENSENSE, INC.
- Current Assignee Address: US CA San Jose
- Agency: Amin, Turocy & Watson
- Main IPC: B81C1/00
- IPC: B81C1/00 ; B81B7/00

Abstract:
A method and system for preparing a semiconductor wafer are disclosed. In a first aspect, the method comprises providing a passivation layer over a patterned top metal on the semiconductor wafer, etching the passivation layer to open a bond pad in the semiconductor wafer using a first mask, depositing a protection layer on the semiconductor wafer, patterning the protective layer using a second mask, and etching the passivation layer to open other electrodes in the semiconductor wafer using a third mask. The system comprises a MEMS device that further comprises a first substrate and a second substrate bonded to the first substrate, wherein the second substrate is prepared by the aforementioned steps of the method.
Public/Granted literature
- US20170066648A1 CMOS-MEMS INTEGRATED DEVICE WITH SELECTIVE BOND PAD PROTECTION Public/Granted day:2017-03-09
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