The present disclosure discloses an enable signal generation circuit, comprising: an input module configured to input a direct current signal from the first input terminal to a first node; a transmission module configured to transmit the direct current signal at the first node to an output terminal; a first conducting module and a second conducting module configured to conduct signals in an alternating current signal from the second input terminal to the first node; a first filter module configured to filter the signal at the first node such that, at the first node, the alternating current signal from the second input terminal is conducted to a common terminal. The second input terminal is connected to the output terminal. The present disclosure simplifies the circuit structure and solves the problem caused by the difference between timing sequences of inputted signals.