Invention Grant
- Patent Title: Integrated circuit packaging substrate, semiconductor package, and manufacturing method
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Application No.: US14622529Application Date: 2015-02-13
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Publication No.: US10043774B2Publication Date: 2018-08-07
- Inventor: Yu-Wei Lin , Chen-Shien Chen , Guan-Yu Chen , Tin-Hao Kuo , Yen-Liang Lin
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Maschoff Brennan
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/498 ; H01L21/66

Abstract:
An integrated circuit (IC) packaging substrate includes a main body, at least one first conductive line, at least one second conductive line, and at least one protrusion pad. The first conductive line is embedded in the main body. The second conductive line is embedded in the main body. The protrusion pad is disposed on the first conductive line. The protrusion pad protrudes from the main body and is configured to be in electrical contact with a solder portion of a semiconductor chip. A first spacing between the protrusion pad and the second conductive line is determined in accordance with a process deviation of the protrusion pad by the width of the protrusion pad and the width of the first conductive line. Moreover, a semiconductor package having the IC packaging substrate and a manufacturing method of the semiconductor package are also provided.
Public/Granted literature
- US20160240502A1 INTEGRATED CIRCUIT PACKAGING SUBSTRATE, SEMICONDUCTOR PACKAGE, AND MANUFACTURING METHOD Public/Granted day:2016-08-18
Information query
IPC分类: