Invention Grant
- Patent Title: Fabrication method of wafer level packaging semiconductor package with sandwich structure of support plate isolation layer and bonding layer
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Application No.: US15497964Application Date: 2017-04-26
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Publication No.: US10049955B2Publication Date: 2018-08-14
- Inventor: Chiang-Cheng Chang , Meng-Tsung Lee , Jung-Pang Huang , Shih-Kuang Chiu
- Applicant: Siliconware Precision Industries Co., Ltd.
- Applicant Address: TW Taichung
- Assignee: Siliconware Precision Industries Co., Ltd.
- Current Assignee: Siliconware Precision Industries Co., Ltd.
- Current Assignee Address: TW Taichung
- Agency: Mintz Levin Cohn Ferris Glovsky and Popeo, P.C.
- Agent Peter F. Corless; Steven M. Jensen
- Priority: TW101107145A 20120303
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L23/31 ; H01L21/56 ; H01L23/00 ; H01L21/78 ; H01L23/538

Abstract:
A fabrication method of a semiconductor package includes the steps of: forming a release layer on a carrier having concave portions; disposing chips on the release layer in the concave portions of the carrier; forming an encapsulant on the chips and the release layer; forming a bonding layer on the encapsulant; removing the release layer and the carrier so as to expose the active surfaces of the chips; and forming a circuit structure on the encapsulant and the chips. Since the release layer is only slightly adhesive to the chips and the encapsulant, the present invention avoids warpage of the overall structure during a thermal cycle caused by incompatible CTEs.
Public/Granted literature
- US20170229364A1 FABRICATION METHOD OF SEMICONDUCTOR PACKAGE Public/Granted day:2017-08-10
Information query
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