Invention Grant
- Patent Title: Low-density parity-check apparatus and operation method thereof
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Application No.: US15379454Application Date: 2016-12-14
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Publication No.: US10050643B2Publication Date: 2018-08-14
- Inventor: Ying Yu Tai , Jiangli Zhu
- Applicant: VIA Technologies, Inc.
- Applicant Address: TW New Taipei
- Assignee: VIA Technologies, Inc.
- Current Assignee: VIA Technologies, Inc.
- Current Assignee Address: TW New Taipei
- Agency: JCIPRNET
- Main IPC: H03M13/00
- IPC: H03M13/00 ; H03M13/25 ; H03M13/37 ; G06F11/10

Abstract:
The LDPC apparatus includes an LDPC iteration calculating circuit, a decision-bit storage circuit, and a convergence detection circuit. The LDPC iteration calculating circuit performs an LDPC iteration calculation to obtain a new decision bit value of a corresponding variable node. The decision-bit storage circuit uses the new decision bit value to update one corresponding old decision bit value among a plurality of old decision bit values. The convergence detection circuit stores check sums of a plurality of check nodes. The convergence detection circuit uses the new decision bit value and the corresponding old decision bit value to update one corresponding check sum among the check sums. The convergence detection circuit determines whether the LDPC iteration calculation is converged based on the check sums of the check nodes.
Public/Granted literature
- US20180167087A1 LOW-DENSITY PARITY-CHECK APPARATUS AND OPERATION METHOD THEREOF Public/Granted day:2018-06-14
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