- 专利标题: Gate cut integration and related device
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申请号: US15430647申请日: 2017-02-13
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公开(公告)号: US10056469B1公开(公告)日: 2018-08-21
- 发明人: Hui-feng Li , Laertis Economikos
- 申请人: GLOBALFOUNDRIES Inc.
- 申请人地址: KY Grand Cayman
- 专利权人: GLOBALFOUNDRIES INC.
- 当前专利权人: GLOBALFOUNDRIES INC.
- 当前专利权人地址: KY Grand Cayman
- 代理机构: Ditthavong & Steiner, P.C.
- 主分类号: H01L29/66
- IPC分类号: H01L29/66 ; H01L21/762 ; H01L21/3065 ; H01L21/3105 ; H01L21/02
摘要:
A method for forming gate cuts during RMG processing and the resulting device are provided. Embodiments include forming Si fins over a substrate; forming a STI layer over the substrate and recessed, exposing upper portions of the Si fins; forming polysilicon dummy gate electrodes perpendicular to the Si fins, separated by STI regions, on the upper portions of the Si fins and on the STI layer between the Si fins; forming a hardmask over the polysilicon dummy gate electrodes; etching through the hardmask and polysilicon dummy gate electrodes forming cavities between some of the Si fins; oxidizing polysilicon exposed on sides of the cavities and any residual polysilicon remaining at a bottom of one or more of the cavities; filling the cavities with SiN; removing the polysilicon dummy gate electrodes; and forming RMGs.
公开/授权文献
- US20180233579A1 GATE CUT INTEGRATION AND RELATED DEVICE 公开/授权日:2018-08-16
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