Invention Grant
- Patent Title: Apparatuses and methods for accessing and scheduling between a plurality of row buffers
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Application No.: US15394860Application Date: 2016-12-30
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Publication No.: US10068636B2Publication Date: 2018-09-04
- Inventor: Berkin Akin , Shigeki Tomishima
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: 2SPL Patentanwaelte Part G mbB
- Agent Mani Arabi
- Main IPC: G11C7/22
- IPC: G11C7/22 ; G11C11/4093 ; G11C11/4091 ; G11C11/4094
Abstract:
The present disclosure relates to a dynamic random access memory (DRAM) array, which comprises a plurality of bit lines connectable, respectively, to at least two row buffers of the DRAM array. The two row buffers are respectively connectable to data input/output (I/O) lines and are configured to electrically connect the two row buffers to the bit lines and data I/O lines in a mutually exclusive manner.
Public/Granted literature
- US20180190339A1 APPARATUSES AND METHODS FOR ACCESSING AND SCHEDULING BETWEEN A PLURALITY OF ROW BUFFERS Public/Granted day:2018-07-05
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