A memory array and an integrated circuit are disclosed. The memory array includes first and second banks of memory elements and five switches. Each memory element of the first bank of memory elements is coupled to an upper rail and to a first node, while each memory element of the second bank of memory elements is coupled to a second node and to a lower rail. The first switch is coupled between the first node and the second node; the second switch is coupled between the first node and the lower rail; and the third switch is coupled between the second node and the upper rail. A fourth switch is coupled between the first node and a voltage that is one diode drop above the lower rail, and a fifth switch is coupled between the second node and a voltage that is one diode drop below the upper rail.