Provided are a package-on-package type semiconductor package and a method of fabricating the same. The semiconductor package includes upper package stacked on a lower package and a via provided between the lower and upper packages to electrically connect the lower and upper packages to each other. The lower package includes a lower package substrate, a lower semiconductor chip mounted on the lower package substrate, and a lower mold layer encapsulating the lower semiconductor chip and including an alignment mark. The lower mold layer includes a marking region, which is provided between the via and the lower semiconductor chip, and on which the alignment mark is provided.