In one example embodiment, a system including a plurality of ports, a plurality of vectoring processors, each of the plurality of vectoring processors having a coefficient memory storing vectoring coefficients corresponding to different victim line and disturber line combinations of a plurality of communication paths connected to the plurality of ports, at least one victim line associated with two of the plurality of vectoring processors and a controller, the controller being configured to assign the victim line and disturber line combinations to the memories based on loads associated with the vectoring coefficients.