Invention Grant
- Patent Title: CMOS nanowire structure
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Application No.: US15411095Application Date: 2017-01-20
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Publication No.: US10074573B2Publication Date: 2018-09-11
- Inventor: Seiyon Kim , Kelin J. Kuhn , Tahir Ghani , Anand S. Murthy , Annalisa Cappellani , Stephen M. Cea , Rafael Rios , Glenn A. Glass
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L27/092 ; H01L27/12 ; H01L29/06 ; B82Y10/00 ; H01L29/66 ; H01L29/775 ; H01L21/84 ; H01L29/423 ; H01L29/10 ; H01L29/78
Abstract:
Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance. A second gate electrode stack completely surrounds the discrete channel region of the second nanowire.
Public/Granted literature
- US20170133277A1 CMOS NANOWIRE STRUCTURE Public/Granted day:2017-05-11
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