Gate driving circuit controlling a plurality of transistors with one Q node and display device using the same
Abstract:
A gate driving circuit and a display device using the same are provided. The gate driving circuit includes a first gate driving circuit configured to sequentially generate first and second output voltages and a second gate driving circuit configured to sequentially generate first and second output voltages. The first gate driving circuit and the second gate driving circuit are asymmetrically connected to gate lines. The first output voltage of the first gate driving circuit is supplied to an nth gate line, and the second output voltage of the second gate driving circuit is supplied to the nth gate line.
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