Invention Grant
- Patent Title: Hardware apparatuses and methods to control access to a multiple bank data cache
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Application No.: US15297084Application Date: 2016-10-18
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Publication No.: US10095623B2Publication Date: 2018-10-09
- Inventor: Andrey Kluchnikov , Jayesh Iyer , Sergey Y. Shishlov , Boris A. Babayan
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Nicholson De Vos Webster & Elliott LLP
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/0844 ; G06F12/0875 ; G06F3/06 ; G06F12/0811 ; G06F12/084 ; G06F12/0842 ; G06F13/18 ; G06F9/52

Abstract:
Methods and apparatuses to control access to a multiple bank data cache are described. In one embodiment, a processor includes conflict resolution logic to detect multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle and to grant access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache. In another embodiment, a method includes detecting multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle, and granting access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache.
Public/Granted literature
- US20170039139A1 HARDWARE APPARATUSES AND METHODS TO CONTROL ACCESS TO A MULTIPLE BANK DATA CACHE Public/Granted day:2017-02-09
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