Invention Grant
- Patent Title: High-speed receiver architecture
-
Application No.: US15839380Application Date: 2017-12-12
-
Publication No.: US10097273B2Publication Date: 2018-10-09
- Inventor: Oscar Ernesto Agazzi , Diego Ernesto Crivelli , Hugo Santiago Carrer , Mario Rafael Hueda , German Cesar Augusto Luna , Carl Grace
- Applicant: INPHI CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INPHI CORPORATION
- Current Assignee: INPHI CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Ogawa P.C.
- Agent Richard T. Ogawa
- Main IPC: H04B1/38
- IPC: H04B1/38 ; H04L5/16 ; H04B10/50 ; H04B7/005 ; H04L25/02 ; H04B3/23 ; H03M13/41 ; H04B10/2507 ; H04B10/294 ; H04B10/69 ; H04B1/04 ; H04B10/40 ; H04B7/0456

Abstract:
A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decorder, for example, a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.
Public/Granted literature
- US20180102850A1 HIGH-SPEED RECEIVER ARCHITECTURE Public/Granted day:2018-04-12
Information query