Invention Grant
- Patent Title: Embedded shape sige for strained channel transistors
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Application No.: US15664225Application Date: 2017-07-31
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Publication No.: US10103245B2Publication Date: 2018-10-16
- Inventor: John H. Zhang , Pietro Montanini
- Applicant: STMicroelectronics, Inc.
- Applicant Address: US TX Coppell
- Assignee: STMicroelectronics, Inc.
- Current Assignee: STMicroelectronics, Inc.
- Current Assignee Address: US TX Coppell
- Agency: Seed IP Law Group LLP
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/78 ; H01L21/265 ; H01L21/8238 ; H01L27/092 ; H01L29/10 ; H01L29/165

Abstract:
An integrated circuit die includes a silicon substrate. PMOS and NMOS transistors are formed on the silicon substrate. The carrier mobilities of the PMOS and NMOS transistors are increased by introducing tensile stress into the channel regions of the NMOS transistors and compressive stress into the channel regions of the PMOS transistors. Tensile stress is introduced by including a region of SiGe below the channel region of the NMOS transistors. Compressive stress is introduced by including regions of SiGe in the source and drain regions of the PMOS transistors.
Public/Granted literature
- US20170352741A1 NOVEL EMBEDDED SHAPE SIGE FOR STRAINED CHANNEL TRANSISTORS Public/Granted day:2017-12-07
Information query
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