Invention Grant
- Patent Title: Semiconductor package having an isolation wall to reduce electromagnetic coupling
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Application No.: US15267455Application Date: 2016-09-16
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Publication No.: US10110170B2Publication Date: 2018-10-23
- Inventor: Margaret A. Szymanowski , Sarmad K. Musa , Fernando A. Santos , Mahesh K. Shah
- Applicant: Freescale Semiconductor, Inc.
- Applicant Address: US TX Austin
- Assignee: NXP USA, INC.
- Current Assignee: NXP USA, INC.
- Current Assignee Address: US TX Austin
- Main IPC: H03F1/02
- IPC: H03F1/02 ; H01L23/495 ; H01L23/552 ; H03F3/213 ; H01L23/31 ; H01L23/492 ; H01L23/66 ; H03F3/195 ; H01L21/48 ; H01L23/00 ; H01L25/065 ; H01L25/00 ; H03F3/21

Abstract:
A system and method for packaging a semiconductor device that includes a wall to reduce electromagnetic coupling is presented. A semiconductor device has a substrate on which a first circuit and a second circuit are formed proximate to each other. An isolation wall of electrically conductive material is located between the first circuit and the second circuit, the isolation wall being configured to reduce inductive coupling between the first and second circuits during an operation of the semiconductor device. Several types of isolation walls are presented.
Public/Granted literature
- US20170005621A1 SEMICONDUCTOR PACKAGE HAVING AN ISOLATION WALL TO REDUCE ELECTROMAGNETIC COUPLING Public/Granted day:2017-01-05
Information query
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