Invention Grant
- Patent Title: Semiconductor device and method of forming conductive vias by backside via reveal with CMP
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Application No.: US14316561Application Date: 2014-06-26
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Publication No.: US10115701B2Publication Date: 2018-10-30
- Inventor: Xing Zhao , Duk Ju Na , Siew Joo Tan , Pandi C. Marimuthu
- Applicant: STATS ChipPAC, Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Atkins and Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/00 ; H01L21/78 ; H01L21/768 ; H01L25/00

Abstract:
A semiconductor device has a semiconductor wafer and a conductive via formed through the semiconductor wafer. A portion of the semiconductor wafer is removed such that a portion of the conductive via extends above the semiconductor wafer. A first insulating layer is formed over the conductive via and semiconductor wafer. A second insulating layer is formed over the first insulating layer. The first insulating layer includes an inorganic material and the second insulating layer includes an organic material. A portion of the first and second insulating layers is removed simultaneously from over the conductive via by chemical mechanical polishing (CMP). Alternatively, a first insulating layer including an organic material is formed over the conductive via and semiconductor wafer. A portion of the first insulating layer is removed by CMP. A conductive layer is formed over the conductive via and first insulating layer. The conductive layer is substantially planar.
Public/Granted literature
- US20150380339A1 Semiconductor Device and Method of Forming Conductive Vias by Backside Via Reveal with CMP Public/Granted day:2015-12-31
Information query
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