Invention Grant
- Patent Title: Instruction and logic for identifying instructions for retirement in a multi-strand out-of-order processor
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Application No.: US15103765Application Date: 2013-12-23
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Publication No.: US10133582B2Publication Date: 2018-11-20
- Inventor: Nikolay Kosarev , Sergey Y. Shishlov , Jayesh Iyer , Alexander V. Butuzov , Boris A. Babayan , Andrey Kluchnikov
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alliance IP, LLC
- International Application: PCT/IB2013/003083 WO 20131223
- International Announcement: WO2015/097494 WO 20150702
- Main IPC: G06F9/38
- IPC: G06F9/38 ; G06F9/30

Abstract:
A processor includes a first logic to execute an instruction stream out-of-order, the instruction stream divided into a plurality of strands, the instruction stream and each strand ordered by program order (PO). The processor also includes a second logic to determine an oldest undispatched instruction in the instruction stream and store an associated PO value of the oldest undispatched instruction as an executed instruction pointer. The instruction stream includes dispatched and undispatched instructions. The processor also includes a third logic to determine a most recently retired instruction in the instruction stream and store an associated PO value of the most recently retired instruction as a retirement pointer, a fourth logic to select a range of instructions between the retirement pointer and the executed instruction pointer, and a fifth logic to identify the range of instructions as eligible for retirement.
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Information query