Invention Grant
- Patent Title: Method and apparatus for selective and power-aware memory error protection and memory management
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Application No.: US14684368Application Date: 2015-04-11
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Publication No.: US10141955B2Publication Date: 2018-11-27
- Inventor: Carlos H. Andrade Costa , Chen-Yong Cher , Yoonho Park , Bryan S. Rosenburg , Kyung D. Ryu
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Hoffmann & Baron, LLP
- Agent Daniel P. Morris, Esq.
- Main IPC: H03M13/35
- IPC: H03M13/35 ; G06F11/10 ; H03M13/51

Abstract:
A method for providing selective memory error protection responsive to a predictable failure notification associated with at least one portion of a memory in a computing system includes: obtaining an active error correcting code (ECC) configuration corresponding to the portion of the memory; determining whether the active ECC configuration is sufficient to correct at least one error in the portion of the memory affected by the predictable failure notification; when the active ECC configuration is insufficient to correct the error, determining whether data corruption can be tolerated by an application running on the computing system; when data corruption cannot be tolerated by the application, determining whether a stronger ECC level is available and, if a stronger ECC level is available, increasing a strength of the active ECC configuration; and when data corruption can be tolerated, performing page reassignment and aggregation of non-critical data.
Public/Granted literature
- US20160301428A1 METHOD AND APPARATUS FOR SELECTIVE AND POWER-AWARE MEMORY ERROR PROTECTION AND MEMORY MANAGEMENT Public/Granted day:2016-10-13
Information query
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