- 专利标题： Systems, processes and computer-accessible medium for providing logic encryption utilizing fault analysis
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申请号： US14797841申请日： 2015-07-13
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公开(公告)号： US10153769B2公开(公告)日： 2018-12-11
- 发明人: Ozgur Sinanoglu , Youngok Pino , Jeyavijayan Rajendran , Ramesh Karri
- 申请人： New York University
- 申请人地址： US NY New York
- 专利权人： New York University
- 当前专利权人： New York University
- 当前专利权人地址： US NY New York
- 代理机构： Hunton Andrews Kurth LLP
- 主分类号： G06F17/50
- IPC分类号： G06F17/50 ; H03K19/003 ; G09C1/00 ; H04L9/08
摘要：
Exemplary systems, methods and computer-accessible mediums can encrypting a circuit by determining at least one location to insert at least one gate in the circuit using a fault analysis, and inserting the at least one gate in at least one section of the at least one location. The determination can include an iterative procedure that can be a greedy iterative procedure. The determination can be based on an effect of the particular location on a maximum number of outputs of the circuit.
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