An integrated circuit comprising at least one logic tile, wherein at least one logic tile includes a mesh interconnect network. The mesh network includes (i) a plurality of interconnected multiplexers, wherein each multiplexer includes inputs, an output, and a plurality of selection inputs to receive signals that control whether an input is connected to the output and (ii) an inactive/static multiplexer which includes inputs, an output that is inactive/static, and a plurality of selection inputs to receive signals that control whether an input of the inactive/static multiplexer is connected to the output wherein such output is connected to an input of at least one of the interconnected multiplexers of the mesh network. In operation, the selection signals applied to the selection inputs of the inactive/static multiplexer are programmed to concurrently connect two or more inputs to the output of the inactive/static multiplexer.