- 专利标题: 3D IC bump height metrology APC
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申请号: US15831806申请日: 2017-12-05
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公开(公告)号: US10181415B2公开(公告)日: 2019-01-15
- 发明人: Nai-Han Cheng , Chi-Ming Yang
- 申请人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 申请人地址: TW Hsin-Chu
- 专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人地址: TW Hsin-Chu
- 代理机构: Eschweiler & Potashnik, LLC
- 主分类号: G01B11/02
- IPC分类号: G01B11/02 ; G01B11/24 ; H01L21/67 ; G01B11/16 ; G01B11/14 ; H01L21/66 ; H01L23/00 ; H01L21/768 ; H01L25/00 ; H01L25/065
摘要:
In some embodiments, the present disclosure relates to a method of bump metrology The method is performed by forming a through-substrate-via within a substrate, forming a plurality of metal interconnect layers within a dielectric structure over the substrate, and forming a bump on the plurality of metal interconnect layers. One or more substrate warpage parameters of the substrate are measured and an initial position of a lens within a substrate metrology module is calculated based upon the one or more substrate warpage parameters. The lens is then moved to the initial position, and a height and a width of the bump are measured using the substrate metrology module after moving the lens to the initial position.
公开/授权文献
- US20180096872A1 3D IC BUMP HEIGHT METROLOGY APC 公开/授权日:2018-04-05
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