A gate driver includes stages configured to output gate signals and gate initialization signals. Here, an Nth stage includes a first output block configured to generate an Nth carry signal based on an N−1th carry signal and to generate an Nth gate initialization signal based on the N−1th carry signal, an output enable signal, and an output disable signal that is an inverted signal of the output enable signal; and a second output block configured to generate an Nth gate signal by shifting the Nth gate initialization signal by a horizontal time, where N is a positive integer.