Invention Grant
- Patent Title: Enabling low resistance gates and contacts integrated with bilayer dielectrics
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Application No.: US15893232Application Date: 2018-02-09
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Publication No.: US10204828B1Publication Date: 2019-02-12
- Inventor: Ruqiang Bao , Benjamin D. Briggs , Lawrence A. Clevenger , Koichi Motoyama , Cornelius Brown Peethala , Michael Rizzolo , Gen Tsutsui
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Otterstedt, Ellenbogen & Kammer, LLP
- Agent Vazken Alexanian
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/528 ; H01L23/532

Abstract:
A method for forming a semiconductor structure using first and second conductive materials, and having first and second trenches with first and second critical dimensions. The second conductive material exhibits a lower resistivity than the first conductive material at a film thickness corresponding to the second critical dimension and the second conductive material exhibits a higher resistivity than the first conductive material at a film thickness corresponding to the first critical dimension. An initial semiconductor structure has the first trench having the first critical dimension and the second trench having the second critical dimension. The second critical dimension is larger than the first critical dimension. A first conductive structure made from one of the first and second conductive materials is formed in the first trench. A second conductive structure made from another of the first and second conductive materials is formed in the second trench.
Information query
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