Invention Grant
- Patent Title: Polysilicon thin film transistor and manufacturing method thereof, array substrate
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Application No.: US15340524Application Date: 2016-11-01
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Publication No.: US10211229B2Publication Date: 2019-02-19
- Inventor: Zuqiang Wang
- Applicant: BOE TECHNOLOGY GROUP CO., LTD. , ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
- Applicant Address: CN Beijing CN Ordos, Inner Mongolia
- Assignee: BOE TECHNOLOGY GROUP CO., LTD.,ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
- Current Assignee: BOE TECHNOLOGY GROUP CO., LTD.,ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
- Current Assignee Address: CN Beijing CN Ordos, Inner Mongolia
- Agency: Ladas & Parry LLP
- Agent Loren K. Thompson
- Priority: CN201310068300 20130305
- Main IPC: H01L29/786
- IPC: H01L29/786 ; H01L27/12 ; H01L21/02 ; H01L21/265 ; H01L21/324 ; H01L29/66

Abstract:
A polysilicon thin film transistor, a manufacturing method thereof, an array substrate involve display technology field, and can repair the boundary defect and the defect state in polysilicon, suppress the hot carrier effect and make the characteristics of TFTs more stable. The polysilicon thin film transistor includes a gate electrode, a source electrode, a drain electrode and an active layer, the active layer comprises at least a channel area, first doped regions, second doped regions and heavily doped regions, and the first doped regions are disposed on two sides of the channel area, the second doped regions are disposed on sides of the first doped regions away from the channel area; the heavily doped regions are disposed on sides of the second doped regions opposed to the first doped regions; and dosage of ions in the heavily doped regions lies between that in the first doped regions and that in the second doped regions.
Public/Granted literature
- US20170047352A1 POLYSILICON THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE Public/Granted day:2017-02-16
Information query
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