A display panel including a first base substrate including a display area and a peripheral area adjacent to the display area, a signal line disposed on the first base substrate and disposed in the display area, a thin film transistor disposed on the first base substrate and disposed in the display area, a verification code part including a metal layer, the metal layer disposed on the first base substrate and disposed in the peripheral area; a second base substrate facing the first base substrate, and a light blocking layer overlapped with the peripheral area in a plan view, in which the metal layer includes a code portion having an identification mark, and a peripheral portion adjacent to the code portion, and the light blocking layer overlaps at least the peripheral portion of the metal layer in a plan view.