Invention Grant
- Patent Title: Providing hardware-based translation lookaside buffer (TLB) conflict resolution in processor-based systems
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Application No.: US15636434Application Date: 2017-06-28
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Publication No.: US10228991B2Publication Date: 2019-03-12
- Inventor: Samar Asbe , Thomas Philip Speier
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Withrow & Terranova, PLLC
- Main IPC: G06F12/10
- IPC: G06F12/10 ; G06F11/07 ; G06F12/1036 ; G06F12/0806 ; G06F12/1027

Abstract:
Providing hardware-based translation lookaside buffer (TLB) conflict resolution in processor-based systems is disclosed. In this regard, in one aspect, a memory system provides a memory management unit (MMU) and multiple hierarchical page tables, each comprising multiple page table entries comprising corresponding translation preference indicators. The memory system further includes a TLB comprising multiple TLB entries each configured to cache a page table entry. The MMU determines whether a TLB conflict exists between a first TLB entry caching a first page table entry comprising a translation preference indicator that is set and a second TLB entry caching a second page table entry comprising a translation preference indicator that is not set. If so, the MMU selects the first TLB entry for use in a virtual-to-physical address translation operation, based on the translation preference indicator of the first page table entry cached by the first TLB entry being set.
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Information query