Invention Grant
- Patent Title: Systems and methods for leveraging path delay variations in a circuit and generating error-tolerant bitstrings
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Application No.: US14913454Application Date: 2014-08-28
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Publication No.: US10230369B2Publication Date: 2019-03-12
- Inventor: James Plusquellic , James Aarestad
- Applicant: STC.UNM
- Applicant Address: US NM Albuquerque
- Assignee: STC.UNM
- Current Assignee: STC.UNM
- Current Assignee Address: US NM Albuquerque
- Agency: Valauskas Corder LLC
- International Application: PCT/US2014/053276 WO 20140828
- International Announcement: WO2015/031683 WO 20150305
- Main IPC: H05B33/08
- IPC: H05B33/08 ; H03K19/003 ; H03K19/21 ; H03K3/84 ; H03K23/00
Abstract:
A Hardware-Embedded Delay PUF (HELP) leverages entropy by monitoring path stability and measuring path delays from core logic macros. HELP incorporates techniques to deal with bias. A unique feature of HELP is that it may compare data measured from different test structures. HELP may be implemented in existing FPGA platforms. HELP may leverage both path stability and within-die variations as sources of entropy.
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