Invention Grant
- Patent Title: Word line read disturb error reduction through fine grained access counter mechanism
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Application No.: US15627928Application Date: 2017-06-20
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Publication No.: US10236069B2Publication Date: 2019-03-19
- Inventor: Ning Wu , Robert E. Frickey
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Compass IP Law PC
- Main IPC: G11C16/34
- IPC: G11C16/34 ; G11C16/04 ; G11C11/56 ; G11C11/34

Abstract:
An apparatus is described. The apparatus includes a storage device having multiple non volatile memory chips and controller circuitry. The controller circuitry is to implement wear leveling of storage cells of the non volatile memory chips at a granularity of segments of storage cell arrays of the non volatile memory chips that share a same disturber node and that are coupled to a same storage cell array wire to diminish disturb errors.
Public/Granted literature
- US20180366204A1 WORD LINE READ DISTURB ERROR REDUCTION THROUGH FINE GRAINED ACCESS COUNTER MECHANISM Public/Granted day:2018-12-20
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