Invention Grant
- Patent Title: Error detection and correction utilizing locally stored parity information
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Application No.: US14521183Application Date: 2014-10-22
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Publication No.: US10248497B2Publication Date: 2019-04-02
- Inventor: Prashant Jayaprakash Nair , David A. Roberts
- Applicant: Advanced Micro Devices, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F11/10
- IPC: G06F11/10 ; H03M13/11

Abstract:
A processing system includes a memory coupled to a processor. The memory stores data blocks, with each data block having a separate associated checksum value stored along with the data block in the memory. The processor has a storage location that stores parity information for the data blocks, with the parity information having a plurality of parity blocks. Each parity block represents a parity of a corresponding set of data blocks. The parity blocks can be accessed for use in error detection and correction schemes used by the processing system.
Public/Granted literature
- US20160117221A1 ERROR DETECTION AND CORRECTION UTILIZING LOCALLY STORED PARITY INFORMATION Public/Granted day:2016-04-28
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