- 专利标题: Semiconductor device package with a stress relax pattern
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申请号: US15461465申请日: 2017-03-16
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公开(公告)号: US10249573B2公开(公告)日: 2019-04-02
- 发明人: Ting-Feng Su , Chia-Jen Chou
- 申请人: POWERTECH TECHNOLOGY INC.
- 申请人地址: TW Hsinchu County
- 专利权人: POWERTECH TECHNOLOGY INC.
- 当前专利权人: POWERTECH TECHNOLOGY INC.
- 当前专利权人地址: TW Hsinchu County
- 代理商 Winston Hsu
- 主分类号: H01L23/00
- IPC分类号: H01L23/00 ; H01L23/538 ; H01L21/56 ; H01L21/48 ; H01L23/373 ; H01L23/31
摘要:
A semiconductor device package has a die, a pattern of dielectric material formed on an active surface of the die, a plurality of metal contacts electrically connected to the die and surrounded by the pattern, a mold compound formed around the pattern, the die and the metal contacts, and a redistribution layer formed on a grinded surface of the mold compound and electrically connected to the metal contacts. The dielectric material has a young's modulus lower than a young's modulus of the mold compound, and the dielectric material has a coefficient of thermal expansion lower than a coefficient of thermal expansion of the mold compound.
公开/授权文献
- US20180269160A1 Semiconductor device package with a stress relax pattern 公开/授权日:2018-09-20
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