According to one embodiment, a memory system includes a first memory including a message queue having first to nth addresses (n≥2, n is natural number), a first pointer showing one of the first to nth addresses, and a second pointer showing one of the first to nth addresses, a monitor unit which detects whether the first and second pointers show the first address, and a processing unit which changes an address shown by the first pointer from the first address to an ith address (n≥i≥2, i is natural number) when the first and second pointers show the first address. An address shown by the second pointer is incremented from the first address to a (j+1)th address (j≥1, j is natural number) when first to jth messages are queued in the first to jth addresses.