Invention Grant
- Patent Title: System and method for multi-patterning
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Application No.: US14967061Application Date: 2015-12-11
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Publication No.: US10268791B2Publication Date: 2019-04-23
- Inventor: Yen-Hung Lin , Chung-Hsing Wang , Chin-Chou Liu , Chi-Wei Hu
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Maschoff Brennan
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A method is disclosed that includes the operation below. Vertices in a conflict graph are sorted into a first clique and a second clique, in which the conflict graph corresponds to a layout of a circuit. A first vertex of the vertices is merged with a second vertex of the vertices, to generate a reduced graph, in which the first clique excludes the second vertex, and the second clique excludes the first vertex. A first color pattern of a plurality of color patterns is assigned to a first pattern, corresponding to the first vertex, and a second pattern, corresponding to the second vertex, in the layout according to the reduced graph.
Public/Granted literature
- US20170169154A1 SYSTEM AND METHOD FOR MULTI-PATTERNING Public/Granted day:2017-06-15
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