Invention Grant
- Patent Title: Semiconductor device packages and stacked package assemblies including high density interconnections
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Application No.: US15615665Application Date: 2017-06-06
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Publication No.: US10276382B2Publication Date: 2019-04-30
- Inventor: John Richard Hunt , William T. Chen , Chih-Pin Hung , Chen-Chao Wang
- Applicant: Advanced Semiconductor Engineering, Inc.
- Applicant Address: TW Kaohsiung
- Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee Address: TW Kaohsiung
- Agency: Foley & Lardner LLP
- Agent Cliff Z. Liu
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/108 ; H01L21/768 ; H01L23/04 ; H01L23/48 ; H01L23/485 ; H01L23/528 ; H01L23/00 ; H01L25/065 ; H01L27/108 ; H01L23/16 ; H01L21/56 ; H01L21/683 ; H01L23/538 ; H01L23/31
Abstract:
A semiconductor device package includes an electronic device and a redistribution stack. The redistribution stack includes a dielectric layer disposed over an active surface of the electronic device and defining an opening exposing at least a portion of a contact pad of the electronic device. The redistribution stack also includes a redistribution layer disposed over the dielectric layer and including a trace. A first portion of the trace extends over the dielectric layer along a longitudinal direction adjacent to the opening, and a second portion of the trace is disposed in the opening and extends between the first portion of the trace and the exposed portion of the contact pad. The second portion of the trace has a maximum width along a transverse direction orthogonal to the longitudinal direction, and the maximum width of the second portion of the trace is no greater than about 3 times of a width of the first portion of the trace.
Public/Granted literature
- US20180047571A1 SEMICONDUCTOR DEVICE PACKAGES AND STACKED PACKAGE ASSEMBLIES INCLUDING HIGH DENSITY INTERCONNECTIONS Public/Granted day:2018-02-15
Information query
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