Invention Grant
- Patent Title: Line edge roughness reduction via step size alteration
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Application No.: US15253379Application Date: 2016-08-31
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Publication No.: US10289003B2Publication Date: 2019-05-14
- Inventor: Thomas L. Laidig , Joseph R. Johnson , Christopher Dennis Bencher
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Patterson + Sheridan, LLP
- Main IPC: G03F7/20
- IPC: G03F7/20

Abstract:
An image correction application relating to the ability to apply maskless lithography patterns to a substrate in a manufacturing process is disclosed. The embodiments described herein relate to a software application platform, which corrects non-uniform image patterns on a substrate. The application platform method includes in a digital micromirror device (DMD) installed in an image projection system, the DMD having a plurality of columns, each column having a plurality of mirrors, disabling at least one entire column of the plurality of columns, exposing a first portion of the substrate to a first shot of electromagnetic radiation, exposing a second portion of the substrate to a second shot of electromagnetic radiation, and iteratively translating the substrate a step size and exposing another portion of the substrate to another shot of electromagnetic radiation until the substrate has been completely exposed to shots of electromagnetic radiation.
Public/Granted literature
- US20170068163A1 LINE EDGE ROUGHNESS REDUCTION VIA STEP SIZE ALTERATION Public/Granted day:2017-03-09
Information query
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