Invention Grant
- Patent Title: Reducing transmitter encoding jitter in a C-PHY interface using multiple clock phases to launch symbols
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Application No.: US15332756Application Date: 2016-10-24
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Publication No.: US10289600B2Publication Date: 2019-05-14
- Inventor: Dhaval Sejpal , Shih-Wei Chou , Chulkyu Lee , Ohjoon Kwon , George Alan Wiley
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Loza & Loza LLP
- Main IPC: G06F13/20
- IPC: G06F13/20 ; G06F13/42 ; H04L25/49 ; H04L7/00

Abstract:
A method for error detection in transmissions on a multi-wire interface includes providing a plurality of launch clock signals, including launch clock signals having a different phase shifts, determining a type of transition in signaling state that will occur on each wire of the 3-wire interface at a boundary between two consecutively transmitted symbols, and selecting one of the plurality of launch clock signals to initiate the transition of signaling state on each wire of the 3-phase interface. Selecting one of the plurality of launch clock signals may include selecting a first launch clock signal when the transition in signaling state terminates at an undriven state, and selecting a second launch clock signal when the transition in signaling state begins at an undriven state. An edge in the first launch clock signal may occur before a corresponding edge in the second launch clock signal.
Public/Granted literature
- US20170039163A1 REDUCING TRANSMITTER ENCODING JITTER IN A C-PHY INTERFACE USING MULTIPLE CLOCK PHASES TO LAUNCH SYMBOLS Public/Granted day:2017-02-09
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