The present disclosure proposes a driving circuit. The driving circuit includes a gate-driver on array (GOA) unit at n stages and n scan lines. A scan line is arranged on the GOA unit at every stage. GOA units at any two neighboring stages arranged at both sides of the scan line. The GOA unit near the first clock signal line is connected to the first clock signal line. The GOA unit near the second clock signal line is connected to the second clock signal line. The nth stage GOA unit couples to an (n−1)th stage GOA unit and an (n+1)th stage GOA unit.