Invention Grant
- Patent Title: Forming an isolation barrier in an isolator
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Application No.: US15600664Application Date: 2017-05-19
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Publication No.: US10290532B2Publication Date: 2019-05-14
- Inventor: Alan John Blennerhassett , Bernard Patrick Stenson
- Applicant: Analog Devices Global
- Applicant Address: BM Hamilton
- Assignee: Analog Devices Global
- Current Assignee: Analog Devices Global
- Current Assignee Address: BM Hamilton
- Agency: Wolf, Greenfield & Sacks, P.C.
- Main IPC: H01L21/76
- IPC: H01L21/76 ; H01L21/768 ; H01L21/8238 ; H01L23/522 ; H01L23/528 ; H01L21/8234 ; H01L23/64 ; H01F17/00 ; H01L29/06 ; H01G4/06

Abstract:
Integrated digital isolators comprise a first transformer coil or capacitor plate mounted on an integrated circuit substrate, and separated from a second transformer coil or capacitor plate via an electrically insulating isolation layer. The electrical isolation that is achieved is dependent upon the material and thickness of the isolation layer. In order to reduce the amount of time required for fabrication while still allowing thick isolation layers to be deployed, in examples of the disclosure pre-formed sheets or tapes of dielectric material are applied to the substrate over the first transformer coil or capacitive plate, for example by being rolled onto the substrate using a heated roller. Such a technique results in a thick isolation layer that is formed using a simple process and much more quickly and reliably than conventional spin-coating or deposition techniques.
Public/Granted literature
- US20180337084A1 FORMING AN ISOLATION BARRIER IN AN ISOLATOR Public/Granted day:2018-11-22
Information query
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