A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one first metal layer interconnecting the plurality of first transistors, where the interconnecting includes forming a plurality of logic gates; a plurality of second transistors overlaying the first single crystal layer; a second metal layer overlaying the plurality of second transistors; a plurality of third transistors overlaying the second transistors; a third metal layer overlaying the plurality of third transistors; and a connective metal path between the third metal layer and at least one of the first transistors, where at least one of the plurality of third transistors is aligned to at least one of the plurality of first transistors with less than 40 nm alignment error, where the first metal layer is powered by a first voltage and the second metal layer is powered by a second voltage.