Invention Grant
- Patent Title: System for integrating preceding steps and subsequent steps
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Application No.: US15531237Application Date: 2015-11-16
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Publication No.: US10304675B2Publication Date: 2019-05-28
- Inventor: Michihiro Inoue , Shiro Hara , Fumito Imura , Arami Saruwatari , Sommawan Khumpuang
- Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
- Applicant Address: JP Tokyo
- Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
- Current Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
- Current Assignee Address: JP Tokyo
- Agency: Oliff PLC
- Priority: JP2014-240531 20141127
- International Application: PCT/JP2015/082138 WO 20151116
- International Announcement: WO2016/084643 WO 20160602
- Main IPC: H01L21/677
- IPC: H01L21/677 ; H01L21/673 ; H01L21/02 ; H01L23/00 ; H01L23/544

Abstract:
A semiconductor manufacturing system has a series of steps, from manufacturing of a semiconductor on a wafer until packaging, that can be easily linked. A semiconductor chip manufacturing device manufactures a semiconductor chip, and a semiconductor packaging device packages the semiconductor chip by attaching the semiconductor chip to a package substrate which is larger than the wafer. The semiconductor chip manufacturing device includes a PLAD system for loading the wafer into and out of the semiconductor chip manufacturing device through a shuttle which is capable of housing the wafer. The semiconductor packaging device includes a PLAD system capable of loading the package substrate into and out of the semiconductor packaging device through a shuttle which is capable of housing the package substrate. The shuttles have container bodies of a same shape.
Public/Granted literature
- US20170330741A1 SYSTEM FOR INTEGRATING PRECEDING STEPS AND SUBSEQUENT STEPS Public/Granted day:2017-11-16
Information query
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