Invention Grant
- Patent Title: Pads and pin-outs in three dimensional integrated circuits
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Application No.: US15985590Application Date: 2018-05-21
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Publication No.: US10304854B2Publication Date: 2019-05-28
- Inventor: Raminda Udaya Madurawe
- Applicant: CALLAHAN CELLULAR L.L.C.
- Applicant Address: US DE Wilmington
- Assignee: CALLAHAN CELLULAR L.L.C.
- Current Assignee: CALLAHAN CELLULAR L.L.C.
- Current Assignee Address: US DE Wilmington
- Main IPC: H03K19/177
- IPC: H03K19/177 ; H01L27/118 ; G11C5/06 ; G11C11/413 ; H01L21/28 ; H01L23/48 ; H01L23/36
Abstract:
A three dimensional semiconductor device, comprising: a substrate including a plurality of circuits; a plurality of pads, each pad coupled to a circuit; and a memory array positioned above or below the substrate and coupled to a circuit to program the memory array.
Public/Granted literature
- US20180277549A1 PADS AND PIN-OUTS IN THREE DIMENSIONAL INTEGRATED CIRCUITS Public/Granted day:2018-09-27
Information query
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