Invention Grant
- Patent Title: System and method of speculative parallel execution of cache line unaligned load instructions
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Application No.: US14963154Application Date: 2015-12-08
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Publication No.: US10310859B2Publication Date: 2019-06-04
- Inventor: Qianli Di , Junjie Zhang
- Applicant: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
- Applicant Address: CN Shanghai
- Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
- Current Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
- Current Assignee Address: CN Shanghai
- Agency: McClure, Qualey & Rodack, LLP
- Priority: CN201510794204 20151118
- Main IPC: G06F9/38
- IPC: G06F9/38 ; G06F9/30 ; G06F9/345 ; G06F9/32 ; G06F12/0875

Abstract:
A system and method of performing speculative parallel execution of a cache line unaligned load instruction including speculatively predicting whether a load instruction is unaligned with a cache memory, marking the load instruction as unaligned and issuing the instruction to a scheduler, dispatching the unaligned load instruction in parallel to first and second load pipelines, determining corresponding addresses for both load pipelines to retrieve data from first and second cache lines incorporating the target load data, and merging the data retrieved from both load pipelines. Prediction may be based on matching an instruction pointer of a previous iteration of the load instruction that was qualified as actually unaligned. Prediction may be further based on using a last address and a skip stride to predict a data stride between consecutive iterations of the load instruction. The addresses for both loads are selected to incorporate the target load data.
Public/Granted literature
- US20170139718A1 SYSTEM AND METHOD OF SPECULATIVE PARALLEL EXECUTION OF CACHE LINE UNALIGNED LOAD INSTRUCTIONS Public/Granted day:2017-05-18
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