Invention Grant
- Patent Title: Masked gate logic for resistance to power analysis
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Application No.: US15392961Application Date: 2016-12-28
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Publication No.: US10311255B2Publication Date: 2019-06-04
- Inventor: Andrew John Leiserson , Mark Evan Marson , Megan Anneke Wachs
- Applicant: CRYPTOGRAPHY RESEARCH, INC.
- Applicant Address: US CA Sunnyvale
- Assignee: Cryptography Research, Inc.
- Current Assignee: Cryptography Research, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Lowenstein Sandler LLP
- Main IPC: H04L9/00
- IPC: H04L9/00 ; G06F21/71 ; G06F21/72 ; G06F21/75

Abstract:
A method of and system for gate-level masking of secret data during a cryptographic process is described. A mask share is determined, wherein a first portion of the mask share includes a first number of zero-values and a second number of one-values, and a second portion of the mask share includes the first number of one-values and the second number of zero-values. Masked data values and the first portion of the mask share are input into a first portion of masked gate logic, and the masked data values and the second portion of the mask share are input into a second portion of the masked gate logic. A first output from the first portion of the masked gate logic and a second output from the second portion of the masked gate logic are identified, wherein either the first output or the second output is a zero-value.
Public/Granted literature
- US20170154193A1 GATE-LEVEL MASKING Public/Granted day:2017-06-01
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