Invention Grant
- Patent Title: Stacked electronics package and method of manufacturing thereof
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Application No.: US15343259Application Date: 2016-11-04
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Publication No.: US10312194B2Publication Date: 2019-06-04
- Inventor: Risto Ilkka Tuominen , Arun Virupaksha Gowda
- Applicant: General Electric Company
- Applicant Address: US NY Schenectady
- Assignee: General Electric Company
- Current Assignee: General Electric Company
- Current Assignee Address: US NY Schenectady
- Agency: Ziolkowski Patent Solutions Group, SC
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L25/18 ; H01L25/00 ; H01L23/00 ; H01L25/16

Abstract:
An electronics package includes an insulating substrate, a first electrical component coupled to a top surface of the insulating substrate, and a second electrical component coupled to a bottom surface of the insulating substrate. A first conductor layer is formed on the bottom surface of the insulating substrate and extends through a via formed therethrough to contact a contact pad of the first electrical component, with a portion of the first conductor layer positioned between the insulating substrate and the second electrical component. A second conductor layer is formed on the top surface of the insulating substrate and extends through another via formed therethrough to electrically couple with the first conductor layer and to contact a contact pad of the second electrical component.
Public/Granted literature
- US20180130747A1 STACKED ELECTRONICS PACKAGE AND METHOD OF MANUFACTURING THEREOF Public/Granted day:2018-05-10
Information query
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