Invention Grant
- Patent Title: Flexible architecture and instruction for advanced encryption standard (AES)
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Application No.: US14984616Application Date: 2015-12-30
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Publication No.: US10313107B2Publication Date: 2019-06-04
- Inventor: Shay Gueron , Wajdi K Feghali , Vinodh Gopal , Raghunandan Makaram , Martin G Dixon , Srinivas Chennupaty , Michael E Kounavis
- Applicant: Intel Corporation
- Agency: NDWE, LLP
- Main IPC: H04L9/28
- IPC: H04L9/28 ; G06F21/72 ; H04L9/06 ; H04L9/08 ; G06F12/14 ; G06F21/60 ; G06F12/0875 ; G06F9/30 ; G06F12/0862 ; G06F9/38 ; G11C7/10 ; G06F3/06
Abstract:
A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
Public/Granted literature
- US20160248580A1 FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES) Public/Granted day:2016-08-25
Information query
